What is 'nanostack' architecture?

Nanostack refers to a new way of designing chips where transistors are stacked vertically, rather than just arranged side-by-side on a flat surface. This 3D stacking is crucial for increasing transistor density beyond the limits of traditional 2D scaling, enabling more components in the same footprint.

How will this affect my phone or computer?

Not immediately. This is a laboratory breakthrough that will take years to reach commercial production, likely starting with specialized high-performance applications like AI data centers. It could be a decade or more before the underlying technology influences mainstream consumer devices like phones and PCs, but it lays the groundwork for future generations of these devices to be significantly more powerful and efficient.

Does this mean Moore's Law will continue indefinitely?

It extends the runway for Moore's Law significantly. Many in the industry believed traditional scaling was reaching its limits. Innovations like nanostack architecture, which enable vertical integration, provide a new path to continue increasing transistor density, pushing back the predicted end of Moore's Law for at least another decade, if not longer.

Who will manufacture these chips?

While IBM developed the technology, it typically licenses its foundational chip innovations to major semiconductor foundries for mass production. Companies like TSMC, Samsung Foundry, or Intel Foundry are potential partners that could eventually manufacture these chips at scale, integrating IBM's design principles into their fabrication processes.

Image: courtesy of Ars Technica

techJune 26, 2026By Veridact EditorialUpdated Jun 26

IBM Claims Sub-1 Nanometer Chip Breakthrough, Doubling Transistor Density for Next-Gen AI

IBM announced yesterday it has developed the world's first sub-1 nanometer chip technology, featuring a 0.7 nanometer node with a revolutionary 'nanostack' architecture. This breakthrough allows for the integration of approximately 100 billion transistors onto a chip the size of a human fingernail, nearly doubling the density of IBM's previous 2 nanometer designs. The company expects this technology, which promises significant gains in computing power and energy efficiency, to reach commercial production within the next decade, with profound implications for artificial intelligence and high-performance computing.

Outlook

The immediate consequence for consumers is limited. This is a laboratory breakthrough, not a product ready for mass consumption. However, the technology signals a clear direction for the semiconductor industry. Over the coming years, we can expect to see IBM work towards refining the manufacturing processes and seeking partnerships with major foundries, such as TSMC or Samsung, to bring this technology to scale. The long lead time — 'within the next decade' for commercial production — indicates the immense challenges involved in transitioning from a prototype to a commercially viable chip. The first applications are likely to be in high-performance computing centers and specialized AI accelerators, rather than mainstream consumer devices like smartphones or laptops, where cost and established manufacturing lines often dictate adoption rates.

Background

The significance of IBM's announcement yesterday lies in its aggressive push past current industry benchmarks. The 'nanometer' (nm) figure refers to the size of the transistors and the distance between them on a chip. A smaller number generally means more transistors can be packed into the same area, leading to more powerful and energy-efficient processors. For years, the industry has been chasing ever-smaller nodes, with 5nm and 3nm chips currently at the forefront of commercial production from manufacturers like TSMC and Samsung. IBM itself had previously announced a 2nm chip breakthrough in 2021. The jump to sub-1nm, specifically 0.7nm or 7 angstroms, represents a significant technical hurdle overcome. The 'nanostack' architecture is key to this achievement, allowing transistors to be stacked vertically, rather than just side-by-side, which is essential for increasing density as traditional planar scaling approaches its physical limits. This vertical integration is critical as chipmakers struggle to continue the historical trend of Moore's Law, which predicts a doubling of transistors on a chip roughly every two years.

Precedents

IBM has a long and storied history in semiconductor innovation, frequently announcing significant breakthroughs that push the boundaries of chip technology. The company developed the first DRAM chip in 1966, pioneered copper interconnects in 1997 (which sped up chips by 30%), and was instrumental in developing silicon-on-insulator (SOI) technology. More recently, IBM announced its 2nm chip technology in 2021, which at the time represented a significant leap forward. A consistent pattern for IBM is to lead in fundamental research and development, often creating 'firsts' in chip architecture and manufacturing processes. However, unlike pure-play foundries like TSMC or Intel Foundry, IBM typically does not mass-produce these cutting-edge chips for the broader market itself. Instead, it often licenses its technology or partners with other manufacturers to bring these innovations to commercial scale. This model suggests that while IBM is a critical engine of foundational research, the actual mass production and widespread integration of its sub-1nm technology will likely depend on collaborations with industry partners, mirroring its historical approach.

The race for smaller, more powerful, and more energy-efficient chips is not just about incremental improvements; it underpins the entire digital economy and national security. This breakthrough from IBM changes the conversation around the future trajectory of computing power. For artificial intelligence, which demands immense computational resources, a doubling of transistor density and improved energy efficiency means that more complex models can be run faster, with less power, and potentially at a lower operational cost. This could accelerate advancements in everything from autonomous systems and advanced robotics to drug discovery and climate modeling.

The ability to pack 100 billion transistors onto a fingernail-sized chip effectively extends the viability of Moore's Law, which many analysts have suggested was nearing its physical limits. The 'nanostack' architecture represents a new paradigm, moving beyond simply shrinking components horizontally to building them vertically. This shift is crucial for sustaining the exponential growth in computing power that industries have come to rely on. For governments, leadership in advanced semiconductor technology is a strategic imperative, influencing economic competitiveness and geopolitical standing. This kind of foundational research ensures that the US, where IBM is based, remains at the cutting edge of chip design, even if manufacturing occurs elsewhere.

Scenarios

Analysis

One possible outcome is that IBM successfully partners with one or more leading foundries to transition its 0.7nm nanostack technology from the lab into pilot production lines. This would validate the manufacturing feasibility of the new architecture and accelerate its path to commercialization, potentially seeing specialized chips enter the market for high-end AI applications or data centers within the latter half of the decade. Such a partnership could solidify IBM's position as a key intellectual property provider in advanced chip design.

Another scenario is that the technical hurdles of mass production prove more challenging or costly than anticipated. While the lab demonstration is a critical first step, scaling up such a complex 'nanostack' architecture to high-volume, high-yield manufacturing is a monumental task. This could lead to a longer development timeline, pushing widespread commercial availability beyond the stated 'next decade' or limiting initial applications to highly niche, extremely high-value sectors where cost is less of a barrier. In this outcome, the technology might remain more of a proof-of-concept for longer, influencing future designs but not immediately transforming the market.

A third possibility involves competitive dynamics. Other companies and research institutions are also exploring advanced packaging and 3D stacking techniques. While IBM has claimed the 'first sub-1nm chip,' competitors may develop alternative or complementary approaches that could either rival or integrate with IBM's nanostack. This could lead to a fragmented market for advanced nodes, where different architectures compete for adoption, or potentially foster collaborations that combine various innovations to push the industry forward even faster.

Timeline

1966

First DRAM Chip

IBM develops the first Dynamic Random Access Memory (DRAM) chip, a foundational component for modern computing.

1997

Copper Interconnects

IBM pioneers the use of copper interconnects in chips, replacing aluminum and boosting chip speed by 30%.

2021-05-06

2nm Chip Breakthrough

IBM unveils the world's first 2 nanometer chip technology, capable of fitting 50 billion transistors on a fingernail-sized chip, setting a new benchmark for density.

2026-06-25

Sub-1nm Chip Announcement

IBM announces the world's first sub-1 nanometer chip technology (0.7nm) using a 'nanostack' architecture, fitting 100 billion transistors on a chip.

Within the next decade

Commercial Production Expected

IBM states that its 0.7nm nanostack chip technology is expected to reach commercial production, likely through partnerships or licensing.

Frequently Asked Questions

It means the transistors and the spaces between them are incredibly small, less than one nanometer. Specifically, IBM achieved 0.7 nanometers (7 angstroms). This allows for vastly more transistors to be packed onto a single chip, leading to greater processing power and improved energy efficiency.

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